Can AMD break the CUDA Moat? AMD Advancing AI 2026

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• caveatLack of stable internal GPU clusters is choking software progressc 0.90

  AMD engineers' top complaint is that there are not enough stable GPU clusters for internal development or automated CI testing. This bottleneck blocks software progress and prevents AMD from benefiting from AI coding agents, which each need GPUs of their own.

• claimNvidia pushed HBM4 pin speeds well above spec to erase MI455X's bandwidth leadc 0.85

  Nvidia raised its HBM4 pin speed target to 10.7Gbps for Rubin — 40% above MI455's HBM4 — specifically to close the memory bandwidth gap to AMD. This forces Nvidia into a much higher-quality bin than AMD needs.

• claimCDNA 5 is a convergence toward Nvidia's Hopper architecturec 0.85

  CDNA 5 drops to 32 threads per wave to match Nvidia warps and replaces Infinity Cache plus small L2 with a single 96 MB L2 per fabric die, aligning AMD's memory hierarchy with Nvidia's global-to-L2-to-shared model and easing a longstanding pain point for kernel writers.

• claimgfx1250 speaks NVFP4 natively, a first for AMDc 0.85

  MI455X's gfx1250 target executes NVFP4 natively — ROCm's WMMAMatrixScaleFormat enum exposes e8, e5m3, and e4m3 — and AMD has already shipped a gfx1250 NVFP4 GEMM in AITER with runtime dispatch, something CDNA4 (MI355X) cannot do.

• claimROCm is moving fast, but the frontier is moving fasterc 0.85

  The story is no longer that ROCm is broken — it's that ROCm is finally shipping with real urgency while Nvidia's stack keeps pulling ahead, so catch-up feels perpetual even as software quality has massively improved.

• caveatvLLM gating regressed because leadership pulled clusters from the teamc 0.85

  AMD engineers were on track to hit 90% CUDA gating parity by Advancing AI, but leadership pulled clusters away from the internal vLLM team and gating progress massively regressed — while gating pass rate, not the non-gating number leadership publicizes, is what actually matters.

• claimAMD closed the disaggregated inference gap that lingered for monthsc 0.85

  After months of trailing Nvidia on DeepSeek R1 disaggregated inference, AMD has now reached competitive performance, achieving Day 0 disagg support on MiniMax M3 FP4 versus a multi-month lag on the first public recipe in January.

• caveatGenerating kernels is easy — trusting the numbers is notc 0.85

  The real engineering in agentic kernel workflows is anti-cheat: GEAK had to stop scoring the unpatched baseline, add a mode that strips agent edits to the test harness, and Apex ships a tamper detector for hardcoded PASS prints and banned library shortcuts.

• implicationAMD should upstream, not build an AMD-only islandc 0.85

  ATOM and AITER only matter if they improve the mainstream ecosystem; the correct strategy is upstreaming kernels, hardening CI, publishing recipes, and making FP4 + WideEP + disagg + cache offload compose in vLLM and SGLang by default.

• claimAMD optimizations arrive late, land fragile, and need another turnc 0.85

  Days after merging, a maintainer flagged AMD's upstream PR for breaking CI and asked for it to be reverted. That is the broader ROCm inference story in miniature: ingredients are increasingly there, but too many key optimizations arrive late, land fragile, and need another turn before customers can trust them by default.

• implicationThe gimped Meta variant will hand TBD Lab's LLM workloads to Rubinc 0.80

  The half-size MI455 is uncompetitive for scale-up LLM training and inference versus Rubin. Unless AMD works directly with TBD Lab to swap in the standard MI455, AMD will lose its Meta volume for frontier training.

• claimLacking its own scale-up switch puts AMD's roadmap at partner riskc 0.80

  Unlike Nvidia, AMD has no in-house scale-up switch and depends on Broadcom as the sole merchant option shipping a 100T 200G-SerDes switch. This blocks true rack-level co-design and complicates cross-vendor logistics.

• caveatAMD's software composability problem is not fully solvedc 0.80

  AMD has made progress on disagg, FP4, WideEP, and DP-attention individually, but historically combining them broke the stack — a March 2026 DeepSeek-R1 case had DP-attention disagg configs failing GSM8K at near zero while no-DPA passed at over 95%.

• claimHelios shows the same shape: enablement fast, high-value paths absentc 0.80

  Across every layer of the Helios (gfx1250 / MI455X) stack, single-model arch-enablement and KV-transfer plumbing are landing fast, while WideEP, validation, and wave32-tuned high-value kernels are not there yet.

• claimMI455 is the first chip to ship active Local Silicon Interconnectsc 0.75

  The MI455 is believed to be the first CoWoS-L product shipping with active LSI bridges — silicon interposer bridges that contain live repeater circuitry rather than just passive wiring and capacitors.

• claimMI455X is AMD's first switched rack-scale scale-up deploymentc 0.75

  Helios marks AMD's move from the 8-GPU point-to-point mesh used through MI355X to a switched scale-up domain across an entire rack — a major architectural upgrade.

• caveatAMD inherited the flyover-cable design Nvidia already abandonedc 0.75

  Helios borrows the flyover-cable approach that plagued GB200/GB300 manufacturing. Nvidia has since pivoted to a cableless design for Vera Rubin NVL72, but the change came too late for AMD to adopt in MI455X Helios.

• claimAI training networks suffer from three linked pathologiesc 0.75

  Large training clusters chronically hit elephant flows, low entropy, and suboptimal fabric utilization — long heavy flows congest links, few IP flows leave most of the fabric idle, and the resulting skew forces expensive overprovisioning.

• contextROCm.ai industrializes the Day 0 loopc 0.75

  At Advancing AI 2026 AMD announced ROCm.ai — GEAK for kernel generation, Hyperloom as orchestrator, plus Magpie, TraceLens, Apex, and AgentKernelArena — mapping almost one-to-one onto the agentic Day 0 workflow SemiAnalysis has been running.

• mechanismThe break is at the framework integration layerc 0.75

  SGLang's July 22 gfx1250 nightly only builds and publishes an image — no test job, no accuracy gate, mirrored through an MI300 because no gfx1250 runner exists upstream. It builds MoRI but pins a June commit predating gfx1250 support, so MoRI-EP WideEP does not run because MoRI's build gates only gfx942/gfx950.

• claimAMD had been burning cycles on a downstream RIXL fork for no reasonc 0.75

  AMD was maintaining RIXL as a parallel copy of infrastructure everyone else got for free. The only thing standing between AMD and upstream was whether anyone would try — and NVIDIA had just removed the excuse.

• implicationKV transfer must work in the frameworks people actually deployc 0.75

  NIXL is the transport layer for disaggregated serving, so PD disagg and WideEP become dependable only when KV transfer works on Instinct inside real frameworks, not just inside MoRI. Nobody at AMD should have needed outsiders to point that out.

• mechanismLisa Su's leadership style is what unlocked the turnaroundc 0.70

  The upgrade in outlook rests on AMD having leadership that can drive change rather than committee-style paralysis. Lisa Su personally engaged, implemented outside suggestions, and instilled urgency around software.

• evidenceAnthropic committing 2GW of AMD chips is the market's votec 0.70

  Anthropic has publicly committed to deploying 2GW of AMD accelerators, and its Head of Compute used Claude agentically to bring up its inference stack on AMD hardware — signaling that AMD's open-source stack is viable for frontier labs.

• caveatHelios rack production is stuck in ramp hellc 0.70

  AMD's first rack-scale system uses an older non-cableless tray design, and its weak SerDes forces up to 85% of the backplane to be retimed, requiring over 550 Broadcom retimers per rack. Backplane reliability problems are slowing the ramp.

• evidenceCI parity targets keep slipping because clusters get pulled awayc 0.70

  Kubernetes Pollara NIC CI sits at 0% parity with Nvidia's ConnectX, and vLLM gating regressed after leadership pulled clusters away from the internal vLLM team. The Advancing AI 2026 parity target was missed and pushed to October 2026.

• claimMI455X is the most advanced silicon in the industryc 0.70

  AMD is first to ship 2nm datacenter silicon, uses the largest CoWoS-L module at 5.5x reticle size, and is the only company using TSMC SoIC-X hybrid bonding. The package holds 3,470mm² of logic silicon — far more than anyone else.

• implicationAMD is spending silicon to compensate for microarchitecture weaknessc 0.70

  MI455X delivers 20 PF FP8 vs Rubin's 17.5, but the advantage is mild given how much more silicon is on the package. AMD lacks Rubin's 3-bit LUT tensor cores and must lean on aggressive silicon to make up for microarchitecture, software, and system-design deficits.

• exampleMeta ordered a cut-down MI455 that halves compute and HBMc 0.70

  Most of Meta's MI455 orders are a custom variant with compute silicon halved from 8 dies to 4, HBM dropped from 12 to 6 stacks, and 8-Hi HBM4 instead of 12-Hi. It targets Recsys workloads, mirroring Nvidia's Meta-specific Ariel GB200.

• caveatUsing merchant switches leaves bandwidth strandedc 0.70

  Because AMD relies on Broadcom's TH6, only 432 of 512 200G lanes are used per switch — the rack's aggregate bandwidth doesn't divide evenly among 72 GPUs. Nvidia by contrast co-designed its 28.8T NVSwitch to match 72-GPU racks with zero wastage.

• evidenceHelios needs Ethernet retimers because AMD's SerDes can't clear the copper pathc 0.70

  AMD's 200G SerDes struggles with copper loss between MI455X and the TH6 switch, forcing Broadcom-provided retimers on ~85% of Meta's scale-up links. This adds cost, power, and rack-bring-up complexity that Nvidia's passive Oberon backplane avoids.

• implicationAMD is betting against ever-larger MMA shapesc 0.70

  CDNA 5 barely scales MMA shapes while Nvidia has grown them each generation up to two-SM Blackwell operations, and AMD still lacks weight-compression innovations like Rubin's 3-bit lookup MMA — signalling AMD believes less than Nvidia in the value of scaling multiplication size.

• evidencevLLM CI parity remains incomplete despite real progressc 0.70

  AMD moved stable ROCm support into upstream vLLM and added nightlies, and June and July patches wired up eight gated test groups, but regression dashboards, AITER accuracy gates, disaggregation CI, and automatic performance gating are still roadmap items.

• caveatllm-d Kubernetes parity target for the Pollara NIC was missedc 0.70

  AMD is a founding partner of llm-d, but Pollara NIC coverage sits at 0% parity to ConnectX-7 on llm-d nightly testing because AMD under-invests in internal CI capacity — the Advancing AI 2026 ETA slipped.

• evidenceUpstream fixes have produced order-of-magnitude interactivity gainsc 0.70

  AITER/vLLM fixes upstreamed into vLLM 0.18 delivered up to an 18× interactivity improvement on Kimi K2.5 1T MXFP4 in under 30 days, and AMD's own numbers show a 1.08x–1.2x uplift on baseline frameworks — the right direction because open-source baselines must get faster, not just AMD demos.

• mechanismATOMesh fills the missing distributed-inference gatewayc 0.70

  ATOMesh is a ROCm-native gateway with a Rust routing and orchestration layer handling prefill/decode-disaggregated routing, cache-aware load balancing, and RDMA KV-cache transfer via MoRI-IO or Mooncake, plugging into vLLM and SGLang.

• claimModel value is grit, not intelligencec 0.70

  The productivity gain isn't about model IQ; it's the sheer grit of goal-directed models grinding through tasks in parallel, which is what makes writing and testing OSS serving software no longer a moat.

• contextAgentX benchmark replays real Claude Code and Codex tracesc 0.70

  SemiAnalysis is developing AgentX from ~3 months of internal agent traces, with median ISL/OSL of 140k/396 and a 99.2% infinite-cache hit rate — a workload profile vastly different from the standard 8k1k benchmark.

• contextFrontier MoE architectures make composability urgentc 0.70

  New giant MoEs pin active experts at 4–10 while scaling total experts to 512 and collapse KV to one or two effective heads via MLA — pushing the frontier toward sparser, bandwidth-sensitive, routing-heavy workloads that demand WideEP and distributed scheduling.

• claimOptimizations compose on AMD, but only model- and topology-specificc 0.70

  AMD has shown DeepSeek-V4 disaggregation with DP-attention, EP8, and MTP, plus validated four-node DeepSeek-V4 and Kimi WideEP16 configs. But Kimi DP8/EP8 was excluded after a GPU memory fault and WideEP16 int4 decode must disable HIP graph capture — composition is not dependable by default.

• caveatAMD's MoRI roadmap is owned by only five or six engineersc 0.70

  The H2 2026 MoRI roadmap spans a tiered KV cache (HBM→DRAM→NVMe), SHMEM v2, EP v2 kernels with elastic expert parallelism, mega-kernel codesign, rack-level Helios enablement, and SGLang/vLLM upstreaming. That entire program is reportedly owned by the same handful of engineers.

• claimEvery layer of Helios is missing WideEPc 0.70

  Across PyTorch, kernels, MoRI, frameworks, and ATOM, Helios has arch enablement and the first half of disaggregation — but no WideEP anywhere.

• mechanismActive LSIs let top-die PHYs shrink by regenerating signals mid-channelc 0.65

  TSMC's active bridges regenerate signals along the channel so the top dies no longer carry the full signal-integrity burden. PHYs can shrink, reclaiming leading-edge silicon and shoreline for compute and memory at negligible energy cost.

• evidenceThe RIXL→NIXL upstream landed and hit 341 Gb/s cross-nodec 0.65

  Andy Luo's May 15 PR for ROCm/HIP build support merged June 4 with zero blast radius on the CUDA path, validating end-to-end VRAM transfers over NIXL+UCX on MI300X and MI355X. Follow-up #1647 hit 341 Gb/s cross-node RDMA on two MI355X nodes using AMD's own AINIC RoCE NICs — no Mellanox in the path. RIXL is now fully ported to NIXL and Dynamo core is taking AMD patches.

• evidenceMicrosoft reversing its AMD boycottc 0.60

  Microsoft dropped AMD after MI300X due to bad HBM and poor software, skipping MI325X and MI355X entirely. Its reversal — deploying MI455X Helios, likely for OpenAI on Azure — is a strong signal of restored confidence.

• exampleEquity-rebate deals make Helios effectively free for OpenAIc 0.60

  AMD's stock-option structure gives Meta and OpenAI up to a 105% equity rebate on compute purchases, triggered if AMD stock hits $600 and enough compute is bought. Combined with Helios TCO, cost per million tokens goes practically negative — AMD is essentially giving racks away plus 5%.

• evidenceThe HBM4 push delayed Rubin but suppliers eventually deliveredc 0.60

  Memory suppliers had to rework HBM4 to meet Nvidia's aggressive spec, pushing out Rubin upstream output. Those issues are now resolved, and Vera Rubin will still ship tokens at scale before MI455 Helios.

• claimAMD's edge is how much logic and memory it integrates in one packagec 0.60

  What AMD brings to the table with MI455 is aggressive integration — two base dies, 12 HBM4 stacks, and two IO dies on a single interposer.

• contextMXFP4 and NVFP4 differ mainly in how they carry block scalec 0.60

  Both FP4 formats share the E2M1 element, but MXFP4 uses a 32-element block with a power-of-two E8M0 scale, while NVFP4 uses finer 16-element blocks, an FP8 E4M3 per-block scale, and an FP32 per-tensor scale — costlier but more accurate, and now the default for FP4 checkpoints.

• evidenceDisaggregated inference is becoming a continuously tested featurec 0.60

  SGLang merged a two-node MI355X 1P1D disaggregation nightly for DeepSeek-V4 in FP8 and FP4, then added DP-attention, EP8, MTP, and Kimi K2.6 coverage — a shift from one-off demos to upstream CI.

• mechanismThe Day 0 agent loop pulls recipes, plumbs configs, and self-healsc 0.60

  For each config, a Claude Code or Codex agent pulls the Day 0 recipe, wires it into InferenceX, kicks off sweeps, and on engine errors either fixes and reruns or escalates to a human — all running in parallel across SKUs.

• mechanismHyperloom uses InferenceX numbers as the agent's reward signalc 0.60

  Hyperloom's target_analyzer scrapes InferenceX to set a competitor target the kernel-tuning agent must beat, turning a public leaderboard into an RL-style optimization loop.

• evidenceGEAK has logged real end-to-end wins on shipping siliconc 0.60

  GEAK has produced a verified ~+21.8% end-to-end gain from an MXFP8 decode-bound dense-linear rewrite on MI355X, with honest reporting that grouped-MoE GEMM only reaches roughly a 1.1x ceiling.

• exampleMoRI is a genuine architectural win that still lacks open CIc 0.60

  MoRI is a modular RDMA framework with MoRI-EP for expert dispatch/combine and MoRI-IO for KV transfer, built from first principles by a China-based team and now backed by official ROCm docs for MI355X clusters. The direction is right, but it needs far more open CI and testing.

• evidenceEven AMD's own ATOM engine is disaggregation-first, EP-laterc 0.60

  ATOM's Helios work adds DeepSeek-V4 MoRI-IO write-push KV transfer and a UALink scale-up fabric backend, building the KV-transport half of disaggregation for exactly the model and fabric Helios will run. But it carries no EP dispatch/combine, no MoRI-EP, and no WideEP.

• exampleAn outside analyst had to broker AMD's own upstreamingc 0.60

  In April the authors put the question publicly to Stephen Bates on LinkedIn, offered Anush a direct connection to the NIXL maintainers, raised MoRI/RIXL upstreaming in person at TensorWave's summit, and helped AMD form the relationship with NVIDIA needed to upstream the patches.

• evidenceTwo-batch overlap is a year latec 0.60

  SGLang put two-batch overlap and expert parallelism on its H1 2025 roadmap and now exposes `--enable-two-batch-overlap` with claimed 2× throughput. AMD's November 2025 DeepSeek-on-MI300X writeup still described dual-batch overlap as "still being developed" — table stakes that arrived far too late.

• contextHelios connects 72 GPUs through 12 Tomahawk 6 switches in one tierc 0.55

  Each MI455X has 72 lanes of 200G UALoE for 1.8 TB/s uni-di of scale-up bandwidth, connecting to 12 Broadcom TH6 102.4T switches. Scale-out moves to 800G Vulcano NICs delivering 1.6 Tbit/s per GPU.

• evidenceDirect-attach LPDDR on the accelerator has quietly been droppedc 0.55

  Earlier roadmaps included up to 1TB of LPDDR as second-tier memory on each MI455X's EAM module. That is now gone — likely another consequence of tight memory supply.

• evidenceOver 10,000 differential pairs of copper cable are crammed into the rackc 0.55

  Each rack routes 10,368 differential pairs of copper, plus 1,728 flyover cables around the switch ASICs. Every cable is a potential failure point and makes manufacturing inefficient.

• implicationMI500 will need co-packaged optics to reach a 256-GPU domainc 0.55

  MI500 is expected to extend the scale-up domain to 256 GPUs across three racks. At that reach, copper will likely give way to co-packaged copper or co-packaged/near-packaged optics.

• evidenceScale-out networking costs roughly $8,000 per GPUc 0.55

  On an eight-plane two-layer configuration, the scale-out networking content per MI455X GPU works out to about $8,000, driven by two 800G DR4 modules at the NICs and three 1.6T DR8 modules per GPU.

• contextRoCEv2 is fragile because Ethernet and UDP are lossyc 0.55

  RDMA is highly sensitive to packet loss and congestion, yet RoCEv2 runs over lossy Ethernet and UDP with no built-in recovery, which is what forces schemes like Meta's DSF to layer virtual output queues, cell spraying, and deep-buffer switches on top.

• mechanismBigger staging buffers compensate for smaller waves without warp-group MMAc 0.55

  CDNA 5 gives each thread 1024 registers and 320 KB of LDS, which lets AMD stick with 16x16xK MMA shapes even as wave count grows — sidestepping the warp-group MMA scaling Nvidia had to adopt.

• evidenceROCm's recipe and documentation layer has finally maturedc 0.55

  ROCm inference docs now cover vLLM, SGLang, MoRI, Mooncake and deployment; the vLLM optimization guide covers AITER, attention backends, TP/EP/DP, FP8/FP4 and multi-node scaling; ROCm/MAD publishes blueprints for training, large-EP microbenchmarks, and disaggregated prefill/decode.

• contextHotz's diagnosis: AMD had the leadership but never valued softwarec 0.55

  George Hotz notes AMD's dysfunction wasn't incapable leaders — Lisa Su replied to his first email — but a belief that hyperscalers alone would tolerate bad software; the open question is whether the culture can now actually ship good software.

• mechanismMoRI, Mooncake, and urgency drove the disagg turnaroundc 0.55

  The improvement came from concrete software additions — the MoRI backend for distributed inference and Mooncake enhancements — combined with a distributed inference team working with markedly greater urgency under Hai Xiao.

• contextAFD's real payoff needs superpod interconnects AMD doesn't ship until MI455Xc 0.55

  Attention/feed-forward disaggregation only pays off with rack-scale interconnects, and AMD's superpod-class hardware for that regime isn't available until MI455X.

• evidenceWideEP delivers up to 2.28x per-GPU throughputc 0.55

  Moving DeepSeek-R1 from EP8 on one node to EP64 across 64 GPUs cuts experts per GPU from 32 to 4, freeing HBM for KV cache and enabling bigger batches; NVIDIA reports up to 2.28x higher per-GPU output throughput on DeepSeek-V3.

• evidenceMoRI SGL disagg already beats aggregated by 2–3x on DeepSeek-R1c 0.55

  On InferenceX, DeepSeek-R1 iso-interactivity throughput for MoRI SGL outperforms the aggregated SGL config by 2×–3×, though most AMD disagg configs still barely exceed their single-node counterparts.

• evidenceA concurrency-64 EP bug still cuts GSM8K accuracy by 14 pointsc 0.55

  On DeepSeek-R1 with SGLang's MoRI backend, decode at concurrency 64 drops GSM8K to ~80% versus a ~94% baseline holding at every other concurrency. An earlier catastrophic version — fluent-but-wrong output scoring 0 — was traced to an uninitialized reduce buffer in AITER's FP4 MoE kernel and patched in June, but the ~80% cliff persists.

• evidencePyTorch gfx1250 support is a skeleton with no CIc 0.55

  PyTorch's gfx1250 support merged mid-July as pure build-time arch plumbing gated behind an unreleased ROCm 7.14+, so it's dormant on every shipping wheel. It ships with no gfx1250 CI runner and none of the highest-value paths — Composable Kernel GEMM, SDPA, FP8 grouped GEMM — are wired up.

• evidencevLLM bring-up is credible single-node but not distributedc 0.55

  vLLM's gfx1250 work tests four models on the FFM simulator and early silicon with volatile results, with dedicated perf work only for gpt-oss whose ATOM-parity tuning was reverted "until AITER is ready." MoRI was removed from the build outright.

• caveatMI455X ISA break doubles the testing burdenc 0.50

  Unlike Nvidia's Rubin which reuses Blackwell's ISA, MI455 (gfx1250) is a completely different ISA from MI355 (gfx950), forcing AMD to test entirely separate codepaths and kernels on both — further straining scarce internal capacity.

• example12 stacks of HBM4 give MI455X a memory-capacity leadc 0.50

  The large package fits 12 HBM4 stacks for 432GB per chip versus 288GB on Nvidia and Google's 8-stack designs. Despite a 50% wider bus, MI455X bandwidth (23.3 TB/s) is only barely above Rubin's 22 TB/s.

• context131k GPU cluster uses eight-plane scale-out topologyc 0.50

  In a 131k MI455X cluster, each 800G Vulcano NIC splits into four 200G links so every GPU touches all eight independent planes, with 512 leaf and 256 spine switches per plane totaling 6,144 TH6 switches.

• evidenceMoE kernels are the fastest-moving layerc 0.50

  AMD's aiter and FlyDSL have absorbed well over a hundred gfx1250 PRs since spring — wave32/WMMA GEMMs, MXFP4/A8W4 quant, MLA-v4 attention, TDM atoms — with roughly a quarter closed without merging. The centerpiece is the AMD-native MegaMoE fused expert-parallel flow.

• contextNIXL maintainers opened the door to AMD upstreaming in 2026c 0.50

  At NVIDIA's GTC 2026 Dynamo session, NIXL maintainers said on the record they would accept upstream contributions from AMD's RIXL fork, just as they had from Trainium's Neuron fork.

• exampleTensor Data Mover clones Nvidia's TMAc 0.45

  AMD's TDM moves HBM-to-LDS data without register staging, supporting 5D tiling, bounds checking, and multi-cast into work-group clusters — essentially a rebadged TMA, though its descriptors load from SGPR rather than shared memory.

• contextGating pass rate is the only test metric that mattersc 0.40

  Gating tests block PRs from merging when they fail, so gating parity — not the non-gating pass rate AMD leadership tends to showcase — is the true measure of software quality.

• contextFlexible I/O dies built for the UALink erac 0.40

  MI455X uses two identical I/O dies, each with 72 lanes supporting UALoE, Infinity Fabric, PCIe Gen 6, UALink, and xGMI4. The design is aimed squarely at open UALink-based interconnect ecosystems.

• evidenceBackplane and flyover cabling adds ~$69K of BOM per rackc 0.40

  Total backplane and compute-tray interconnect content per rack sums to $68,928 — $44,352 for the backplane and $24,576 for flyover cables.

• contextScale-out supports up to three Vulcano NICs per GPUc 0.40

  Each MI455X can host up to three Pensando Vulcano 800 NICs for 2.4 Tbit/s of scale-out bandwidth, with a Salina 400 DPU handling the front-end network. The dominant deployment is expected to use two NICs for 1.6 Tbit/s.

• exampleCDNA 5 adds a UE5M3 scale format for wider dynamic rangec 0.40

  CDNA 5 supports unsigned E5M3 scaling, which repurposes the sign bit to drop the minimum representable value from 2^-9 to 2^-17 — proposed as an alternative to NVFP4's per-tensor FP32 scale.

• exampleConcrete upstream fixes by SemiAnalysis + agentsc 0.40

  Agent-assisted contributions include a fused MHC kernel fix for DeepSeek v4 in TRT, a NixlConnector handshake fix for MiniMax M3 disagg, EAGLE3 speculative decoding for AMD MiniMax M3, and FP8 KV cache support on MI300X/MI325X.

• contextNVIDIA refused to help AMD's comm library in 2025c 0.40

  At NVIDIA's GTC 2025 NCCL session, NVIDIA said explicitly it would not help AMD's communication team adapt to the upcoming NCCL refactor and does not participate in AMD's communication development at all.

• contextZuckerberg is already reworking Meta's infra strategy orgc 0.35

  Following prior coverage, Mark Zuckerberg has begun rapidly exploring changes to Meta's infrastructure strategy org culture, leaving room for the MI455 decision to be revisited.

• contextHelios uses six switch trays with symmetric compute-tray placementc 0.35

  Six switch trays keep UALoE signal paths shorter than the nine-tray GB300 NVL72, and placing 9 compute trays above and 9 below the switches gives signals equal travel distance in each direction.

• contextATOMesh is a rework of SGLang's gateway, not a from-scratch buildc 0.35

  Rather than reinvent the wheel, AMD derived ATOMesh from SGLang's sgl-model-gateway and substantially reworked it around ATOM and AMD hardware, keeping routing policy separate from model execution.

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• implicationAMD matches Nvidia's Spectrum-X through open UEC instead of vertical integrationc 0.90 · sim 0.83

  The three Vulcano mechanisms together solve what Nvidia solves with ConnectX plus Spectrum-X adaptive routing, but AMD is doing it on the open UEC standard and a multi-vendor fabric rather than a single-vendor stack.

  overlapped with: Vulcano moves network intelligence from the fabric into the NIC

• claimThe competitive frontier has moved to multi-node disaggregated inferencec 0.90 · sim 0.83

  Single-node aggregated performance is table stakes; the real battle is disaggregated systems where attention and feed-forward can be split across hardware best suited for each, making inference a distributed-systems problem.

  overlapped with: AMD needs the whole distributed stack to move as one system

• mechanismPer-packet spraying raises entropy to fix hash collisionsc 0.85 · sim 0.82

  Traditional ECMP pins each flow to one hashed path, so AI's handful of massive synchronized flows collide and stall some links while others idle; Vulcano sprays packets of the same flow across all paths, yielding 1:1 fabric utilization and millisecond failure recovery.

  overlapped with: Vulcano moves network intelligence from the fabric into the NIC

• mechanismNIC-side ordering removes the buffering tax of packet sprayingc 0.75 · sim 0.83

  Because sprayed packets arrive out of order, the NIC enforces ordering at the message level and writes packets directly into GPU memory as they land, avoiding the go-back-N retransmits and buffer bloat that RoCEv2 normally requires.

  overlapped with: Vulcano moves network intelligence from the fabric into the NIC

• contextDistributed inference is no longer optional for AMDc 0.75 · sim 0.87

  AMD's own ROCm tutorial admits single-node optimization is hitting limits, and ROCm has published official Mooncake PD-disaggregation docs (Dec 2025) and MoRI-based distributed inference docs (Jan 2026). Once the official stack ships xP+yD topologies and KV-transfer frameworks, DI is table stakes, not a side quest.

  overlapped with: AMD needs the whole distributed stack to move as one system

• mechanismAgentic coding multiplies GPU demand nonlinearlyc 0.70 · sim 0.86

  In the old model each engineer needed a couple of GPU nodes; now each engineer runs dozens of coding agents, each of which spawns sub-agents that also need GPUs to test against. AMD's internal capacity is more than an order of magnitude behind Nvidia's and getting worse.

  overlapped with: Agentic engineering directly erodes the CUDA moat

• mechanismPath-aware congestion control targets incast head-of-line blockingc 0.70 · sim 0.82

  The NIC tracks per-path status in real time and shifts traffic before queues build, which specifically attacks the many-senders-one-receiver incast pattern of all-reduce and keeps tail latency low under bursty AI workloads.

  overlapped with: Vulcano moves network intelligence from the fabric into the NIC

• claimVulcano lets the transport model follow the fabric, not the other way aroundc 0.70 · sim 0.86

  The NIC supports switch-based spray, NIC-based spray, and NIC-based source routing, so operators can adapt the transport to whatever fabric they already own — smart switches, dumb commodity switches, or endpoint path control.

  overlapped with: Vulcano moves network intelligence from the fabric into the NIC

• evidenceTimeline gap: AMD is roughly two years behind on disagg + WideEPc 0.70 · sim 0.82

  The open CUDA ecosystem has shipped disaggregated inference plus WideEP since early 2024, while AMD's first public PD-disagg + WideEP recipes only landed in January 2026 via InferenceX.

  overlapped with: AMD needs the whole distributed stack to move as one system

• contextAMD winning does not mean Nvidia losesc 0.50 · sim 0.82

  The AI accelerator pie is growing fast enough that AMD gaining share is compatible with Nvidia continuing to grow revenue massively. The competitive pressure mainly forces Jensen to flatten Nvidia's internal bureaucracy.

  overlapped with: AMD now has a real shot at Nvidia after starting from zero